7df88afab9
Recently the Linux kernel's PTP Hardware Clock interface was expanded to include a "write phase" mode where the clock servo in implemented in hardware. This mode hearkens back to the tradition ntp_adjtime interface, passing a measured offset into the kernel's servo. This patch adds a new configuration option and logic to support the write phase mode. Because the hardware's adjustment bandwidth may be limited, this mode is only activated when the servo reaches SERVO_LOCKED_STABLE state, in order to achieve reasonably fast locking times. Users may control the SERVO_LOCKED_STABLE state by configuring 'servo_offset_threshold' and 'servo_num_offset_values' accordingly. Example configuration file highlights: unicast_listen 1 logSyncInterval 0 logMinDelayReqInterval 0 first_step_threshold 0.001000000 step_threshold 0 clock_servo pi write_phase_mode 1 servo_offset_threshold 50 servo_num_offset_values 10 tsproc_mode raw Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com>
91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
/**
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* @file phc.h
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* @note Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef HAVE_PHC_H
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#define HAVE_PHC_H
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#include "missing.h"
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/**
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* Opens a PTP hardware clock device.
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*
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* @param phc The device to open.
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*
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* @return A valid clock ID on success, CLOCK_INVALID otherwise.
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*/
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clockid_t phc_open(const char *phc);
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/**
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* Closes a PTP hardware clock device.
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*
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* @param clkid A clock ID obtained using phc_open().
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*/
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void phc_close(clockid_t clkid);
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/**
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* Query the maximum frequency adjustment of a PTP hardware clock device.
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*
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* @param clkid A clock ID obtained using phc_open().
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*
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* @return The clock's maximum frequency adjustment in parts per billion.
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*/
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int phc_max_adj(clockid_t clkid);
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/**
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* Queries the number of programmable pins of a PTP hardware clock device.
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*
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* @param clkid A clock ID obtained using phc_open().
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*
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* @return The number of pins supported by the clock.
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*/
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int phc_number_pins(clockid_t clkid);
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/**
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* Configures a pin of a PTP hardware clock device.
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*
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* @param clkid A clock ID obtained using phc_open().
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*
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* @param desc Pointer to a pin descriptor with the 'index', 'func',
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* and 'chan' fields set.
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*
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* @return Zero on success, non-zero otherwise.
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*/
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int phc_pin_setfunc(clockid_t clkid, struct ptp_pin_desc *desc);
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/**
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* Checks whether the given PTP hardware clock device supports PPS output.
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*
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* @param clkid A clock ID obtained using phc_open().
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*
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* @return Zero if PPS output is not supported by the clock, non-zero
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* otherwise.
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*/
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int phc_has_pps(clockid_t clkid);
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/**
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* Checks whether the given PTP hardware clock device supports write phase mode.
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*
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* @param clkid A clock ID obtained using phc_open().
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*
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* @return Zero if write phase mode is not supported by the clock, non-zero
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* otherwise.
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*/
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int phc_has_writephase(clockid_t clkid);
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#endif
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